Configurable thermal and power management for portable computers

ABSTRACT

Improved approaches to providing thermal and power management for a computing device are disclosed. These approaches facilitate intelligent control of a processor&#39;s clock frequency and/or a fan&#39;s speed so as to provide thermal and/or power management for the computing device.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. application Ser.No. 12/321,798, filed Jan. 25, 2009, which is a continuation applicationof U.S. application Ser. No. 11/821,142, filed Jun. 22, 2007, which is adivisional application of U.S. application Ser. No. 11/654,337, filedJan. 17, 2007, which is a continuation application of U.S. applicationSer. No. 10/277,630, filed Oct. 22, 2002, now U.S. Pat. No. 7,167,993,which is a continuation application of U.S. application Ser. No.09/782,680, filed Feb. 12, 2001, now U.S. Pat. No. 6,487,668, which is acontinuation application of U.S. application Ser. No. 09/351,051 filedon Jul. 10, 1999, now U.S. Pat. No. 6,216,235, which is a continuationapplication of U.S. application Ser. No. 08/914,299 filed on Aug. 18,1997, now U.S. Pat. No. 5,974,557, which is a continuation applicationof U.S. application Ser. No. 08/262,754 filed Jun. 20, 1994, now U.S.Pat. No. 5,752,011, the disclosures of all of which are incorporatedherein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a computing device and, moreparticularly, to a method and apparatus for controlling a processor'sclock frequency.

2. Description of the Related Art

It is known that if no user activity has occurred for a period of timethat a portable computer can be placed in a suspend or sleep mode. It isalso known to suspend or slow a computer's processor (e.g.,microprocessor, CPU) when the processor is not actively processing. Thefollowing patents and patent publications are representative of thecurrent state of the art:

U.S. Pat. No. 5,201,059 discloses a sleep mode which is activated whencontrol is given to BIOS or alternatively by incorporating somestatistical analysis of the frequency of BIOS calls. In this patent, thesleep mode either stops the clock or slows it to 4 MHz.

U.S. Pat. No. 5,167,024 discloses a power management system for a laptopcomputer. The power management system operates to disconnect powersources and/or clock signals to various peripheral devices to conservebattery power. The slow mode is entered into when no activity has beendetected for a predetermined period of time.

U.S. Pat. No. 5,218,704 discloses a technique for power conservationbased on real-time sampling of CPU activity. The activity is sampledduring interrupts and when it determines that the CPU may rest, a sleepclock is supplied to the CPU. The detection of an interrupt restores theclock to the fast rate prior to processing the interrupt.

U.S. Pat. No. 5,239,652 discloses a technique for power consumptionwhich disconnects the CPU from the power supply when control logicdetermines the CPU is not actively processing. Thereafter, the CPU isperiodically powered-up to perform housekeeping chores as well as todetermine if normal processing should be resumed.

European patent publication EP-0474963 discloses a sleep mode controllerwhich lowers the CPU clock speed when no input/output operation (whenkeyboard control routine of BIOS executed no input key data in keybuffer, or when CPU is idle and no input key data in the key buffer) isperformed. The system uses a clock generator circuit which produces thelow clock (4 MHz), the high clock (32 MHz) and a slightly slower highclock (16 MHz). A keyboard controller is used to determine which of thehigh clocks is used, with selection being made by the computer user. Thesleep mode controller is disabled if the AC adapter is connected.

U.S. Pat. No. 5,230,055 discloses a portable computer wherein thecomputer is made inoperable when ambient temperature or humidity becometoo high. Here, ambient temperature and humidity are periodicallymonitored.

European patent publication EP-0381021 discloses a power saving systemfor a personal computer. The system operates to allow or stop power tobe supplied to an oscillator based on control data set to a controlregister via a keyboard or software.

U.S. Pat. No. 5,021,679 discloses a power system for a portable computerwherein the supply voltage is varied depending on the current beingsupplied to the computer by the power system. Further, avariable-frequency clock is provided which varies its frequency based onthe supply voltage being produced.

External clocks have been used to provide a computer system with fasterclocks. Here, the faster external clock is substituted for the internalclock of the computer system. U.S. Pat. No. 5,134,703 is illustrative ofan external clock unit which supplies a faster clock to a computerwithout requiring any hardware changes within the computer.

The problem with all the prior solutions to energy conservation is thatthe processors can still overheat. In particular, during prolongedprocessing or activity by a computer's processor, the processor will notenter its sleep mode (if any) and as a result the processor will becomehot and require extensive means to cool the processor to preventoverheating and eventual failure of the processor. Overheating andfailure of the processor can also occur when the computer is used inparticularly hot environmental temperatures, the computer's cooling fanfails, or when cooling of the processor is otherwise inadequate.

Another problem is that with portable computers, manufacturers have toeither use a lower clock frequency (lower than would be used in acomparable desk top computer) for processing or provide a fan forcooling. A lower clock frequency is not satisfactory as users wantmaximum processing power just as they get with a desk top computer.Requiring a portable computer to use a fan for cooling is alsounsatisfactory because it consumes battery energy.

Thus, there is a need for a solution to the above problems which enablesa computing device to maximize its processing speed while, at the sametime, preventing overheating.

SUMMARY

Broadly speaking, the invention relates to novel techniques forproviding thermal and power management for a computing device. Thesetechniques facilitate intelligent control of a processor's clockfrequency and/or a fan's speed so as to provide thermal and/or powermanagement for the computing device.

As a method for managing operation of a computing device (e.g., portablecomputer), where the computing device includes at least a processor anda fan, the fan being operable to cool at least the processor, oneembodiment can, for example, include at least: configuring the portablecomputer for one of a plurality of different power managementconfigurations; monitoring a temperature of the processor; controlling aspeed of the fan based on the configured power management configurationfor the portable computer and based on the monitored temperature of theprocessor; and controlling operational performance of the processorbased on the configured power management configuration for the portablecomputer configured and based on the monitored temperature of theprocessor.

Other aspects and advantages of the invention will become apparent fromthe following detailed description, taken in conjunction with theaccompanying drawings, illustrating by way of example the principles ofthe invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be readily understood by the followingdetailed description in conjunction with the accompanying drawings,wherein like reference numerals designate like structural elements, andin which:

FIG. 1 is a block diagram of a first embodiment of the invention;

FIG. 2 is a graph of an example of the relationship of chip temperatureof a microprocessor and frequency of a clock signal;

FIG. 3 is a block diagram of a second embodiment of the invention;

FIG. 4 is a block diagram of a third embodiment of the invention;

FIG. 5 is a block diagram of a fourth embodiment of the invention;

FIG. 6 is a timing diagram illustrating operation of the fourthembodiment;

FIG. 7 is a block diagram of a fifth embodiment of the invention;

FIG. 8 illustrates a schematic diagram of an embodiment of an activitydetector;

FIG. 9 is a block diagram of a sixth embodiment of the invention; and

FIG. 10 is a block diagram of a seventh embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The invention provides novel techniques for controlling a processor'sclock frequency so as to prevent overheating. In addition to preventingoverheating, the invention attempts to maximize the processing speed ofthe processor. The invention also operates to conserve the amount ofenergy consumed by the processor. Preventing the processor fromoverheating is important because when a processor overheats it no longeroperates properly. Conservation of energy, although of generalimportance for all computing devices, is particularly important forportable computing devices.

The invention monitors a processor's activity and its temperature. Whenthere is no activity for the processor, a slow clock frequency is used,thereby saving power and lowering the thermal heat produced by theprocessor. On the other hand, when there is activity for the processor,a fast clock frequency is used. However, when prolonged activity (i.e.,sustained fast clock frequency) causes the processor's temperature tobecome dangerously high for proper operation, the clock frequency isreduced so as to maintain processing speed at a reduced speed whilepreventing overheating.

Embodiments of the invention are discussed below with reference to FIGS.1-10. However, those skilled in the art will readily appreciate that thedetailed description given herein with respect to these figures is forexplanatory purposes as the invention extends beyond these limitedembodiments.

FIG. 1 is a block diagram of a first embodiment of the invention. Inthis embodiment, a microprocessor 2 has a temperature sensor 4 which isintegral with the microprocessor 2. The temperature sensor 4 is eitherintegrated within the Very Large Scale Integration (VLSI) design of themicroprocessor 2 or placed in contact with the housing or packagethereof. In either case, the temperature sensor 4 is thermally coupledwith the microprocessor 2. Because the temperature sensor 4 is integralor thermally coupled with the microprocessor 2, the temperature sensor 4is very responsive to the temperature changes of the microprocessor 2.The temperature sensor 4 produces a temperature signal 6. Temperaturesensing circuitry is well known and therefore not further described.

The temperature signal 6 is supplied to a voltage-controlled oscillator(VCO) 8. The VCO 8 produces a clock signal 10 which is supplied to aclock input of the microprocessor 2. The VCO 8 operates to producedifferent frequencies for the clock signal 10 depending on the value ofthe temperature signal. In this embodiment, the temperature signal 6 ispreferably an analog voltage signal and the VCO 8 produces the clocksignal 10 based on the value of the analog voltage signal. For example,the temperature signal could be a voltage ranging from zero to fivevolts. In response to the temperature signal 6, the VCO 8 could producethe clock signal with frequencies ranging from 100 MHz to 1 MHz. Thefrequency range is a design choice selected in accordance with thespecific microprocessor being utilized. VCO's are well known andtherefore are not further described.

FIG. 2 is a graph of an example of the relationship of chip temperatureof the microprocessor 2 and clock frequency of the clock signal 10. Theclock frequency varies between a maximum frequency (f_(MAX)) and aminimum frequency (f_(MIN)) for given microprocessor. The minimumfrequency (f_(MIN)) may be zero if the clock signal 10 is notresponsible for refreshing dynamic memory; otherwise, it cannot fallbelow some minimum frequency. Notice that as the chip temperatureincreases beyond some threshold temperature (VTH) (e.g., 120 degreesF.), the frequency of the clock signal 10 will gradually decrease. Bydecreasing the clock frequency in relation to the chip temperature,processing speed can be maximized for a given temperature withoutrisking processor overheating. As the chip temperature become “hot”, theclock frequency is reduced so as to reduce the thermal heat generated bythe microprocessor 2. The profile of the curve for the clock frequencyshown in FIG. 2 is illustrative as other curves may be used. Forexample, the frequency of the clock signal 10 could be controlled sothat the chip temperature is maintained in a more limited temperaturerange. In any case, the profiles of the curves decrease the clockfrequency as the temperature increases.

FIG. 3 is a block diagram of a second embodiment of the invention. Inthis embodiment, the microprocessor 2, temperature sensor 4, thetemperature signal 6, the VCO 8, and the clock signal 10 are similar tothose utilized in the first embodiment. However, this embodiment furtherincludes an activity detector 12, an activity signal 14, a VCOcontroller 16, and a control signal 18. The activity detector 12monitors the microprocessor 2 and/or some related peripheral device(e.g., interrupt controller, keyboard buffer, input/output ports,instruction cache, current instruction, program counter) to determinewhen the microprocessor 2 is actively processing or when processing isneeded. In this case, the activity detector 12 notifies the VCOcontroller 16 that processing is needed with the activity signal 14. Onthe other hand, when no activity exists, the activity detector 12notifies the VCO controller 16 that no processing is needed with theactivity signal 14. The activity signal is preferably a digital signalhaving at least one bit. Activity detection is described in more detailin U.S. Pat. No. 5,201,059; U.S. Pat. No. 5,167,024; U.S. Pat. No.5,218,704; U.S. Pat. No. 5,239,652; and European patent publicationEP-0474963, which are hereby incorporated by reference.

The VCO controller 16 receives the activity signal 14 and thetemperature signal 6. In response to these signals, the VCO controller16 produces the control signal 18 which controls the VCO 8. The controlsignal 18 may be analog or digital depending on the design of the VCO 8.The basic operation of the VCO controller 16 is to cause the VCO 8 toproduce the clock signal 10 for the microprocessor 2 in an intelligentmanner so as to conserve energy and prevent overheating. Namely, if theactivity detector 12 indicates that no processing is needed at a givenpoint in time, then regardless of the temperature detected by thetemperature sensor 4, the VCO controller 16 will cause the VCO 8 toproduce a sleep (or slow) clock. The sleep clock has a frequency nearthe minimum frequency (f_(MIN)). On the other hand, if the activitydetector 12 indicates that processing is needed at this point in time,then the VCO controller 16 will cause the VCO 8 to produce a fast clock.The fast clock is the temperature-regulated maximum frequency such asdiscussed in FIGS. 1 and 2.

The second embodiment is particularly advantageous for portablecomputing devices because it conserves battery life by using a sleepclock when no processing is needed. However, even in the case ofprolonged processing, the embodiment prevents overheating.

FIG. 4 is a block diagram of a third embodiment of the invention. Inthis embodiment, the microprocessor 2 includes a clock regulation unit20 which controls the frequency of the clock used by the microprocessor2 based on chip temperature of the microprocessor 2. Preferably, theclock regulation unit 20 is integrated with circuitry of themicroprocessor 2. Alternatively, the clock regulation unit 20 can beseparate from the circuitry of the microprocessor 2 but neverthelesscoupled thereto.

The clock regulation unit 20 receives an input clock from an oscillator22 and produces an output clock which is used by the microprocessor 2.The clock regulation unit 20 includes a temperature sensor 4, a divider24, a first AND gate 26, a second AND gate 28, an inverter 30 and an ORgate 32. The temperature sensor 4 is as previously described. Thedivider 24 divides the input clock (fast clock) from the oscillator 22to produce a sleep (or slow) clock. For example, if the oscillator 22 isa 100 MHz fixed-frequency oscillator and the divider 24 divides by 100,then the sleep clock would be 1 MHz.

In this embodiment, the temperature sensor 4 produces a digital output.It is assumed that the digital output is normally “0”, but when themicroprocessor 2 becomes “hot”, the digital output becomes “1”. Thedigital output of the temperature sensor 4 together with the logic gates26-32 operate to select either the fast clock or the sleep clock as theoutput clock which is used by the microprocessor 2. In particular, whenthe microprocessor 2 is not “hot”, AND gate 26 is inactivated and ANDgate 28 is activated by inverter 30. Hence, the output clock is the fastclock via AND gate 28 and OR gate 32. On the other hand, when themicroprocessor 2 is “hot”, AND gate 26 is activated and AND gate 28 isinactivated. Accordingly, in this case, the output clock is the sleep(or slow) clock via AND gate 26 and OR gate 32.

FIG. 5 is a block diagram of a fourth embodiment of the invention. Inthis embodiment, the microprocessor 2 includes a clock regulation unit20 which controls the frequency of the clock used by the microprocessor2 based on chip temperature of the microprocessor 2 and processingactivity. The clock regulation unit 20 is preferably integrated withcircuitry of the microprocessor 2.

As with the third embodiment, the clock regulation unit 20 for thefourth embodiment receives the input clock from the oscillator 22 andproduces the output clock which is used by the microprocessor 2. Theclock regulation unit 20 includes the temperature sensor 4, the divider24, the first AND gate 26, the second AND gate 28, and the OR gate 32 asdescribed above with reference to FIG. 4. The divider 24 divides theinput clock (fast clock) from the oscillator 22 to produce a sleepclock. The temperature sensor 4 produces a digital output. Although thedigital output from the temperature sensor 4 is normally “0”, when themicroprocessor 2 becomes “hot”, the digital output becomes “1”. Theactivity detector 12 produces an activity signal as described in thesecond embodiment. Here, the activity signal is a digital signal whichis “high” or “1” when activity is present and “low” or “0” when noactivity is present.

The digital output of the temperature sensor 4 together with theactivity signal from the activity detector 12 and the logic gates 26,28, 32, 34, 36 and 38 operate to select either the fast clock or thesleep clock. In particular, when the microprocessor 2 is not “hot” andactivity is present, the AND gate 36 is activated by the inverter 34 andthe activity signal. The output of AND gate 36 then activates AND gate28 and inverter 38 inactivates AND gate 26. Hence, the output clock isthe fast clock via AND gate 28 and OR gate 32. On the other hand, whenthe microprocessor 2 is “hot”, the AND gate 36 is inactivated by theinverter 34 regardless of the activity signal. The output of AND gate 36inactivates AND gate 28, and inverter 38 activates the AND gate 26. Inthis case, the output clock is the sleep clock via AND gate 26 and ORgate 32.

FIG. 6 is a timing diagram illustrating operation of the fourthembodiment. The output clock (CLK) is a mixture of the fast clockproduced by the oscillator 22 and the sleep clock produced by thedivider 24. The temperature signal is the digital output of thetemperature sensor 4. The temperature signal is “0” while the chiptemperature is not “hot”. However, when the chip temperature becomes“hot”, the temperature signal becomes “1”, as shown at point A. Theactivity signal is “1” when activity is present for processing by themicroprocessor 2; otherwise, the activity signal is “0” to indicate noactivity is present for processing. As shown in FIG. 6, the output clockfollows the fast clock only when the temperature signal is “0” and theactivity signal is “1”; otherwise, the output clock follows the sleepclock. Note that the transitions for the output clock from fast clock tosleep clock and from sleep clock to fast clock are shown as beingsynchronized with the low or “0” portion of the fast clock. For example,at point B the output clock would produce a partial pulse (from the fastclock) if not synchronized. Hence, it is probably preferred thatswitching occur only when the fast clock is “low,” or when both the fastand sleep clocks are “low” as shown at point C. Note that at point C,the output clock transitions from the sleep clock to the fast clock butbecause the transition is synchronized with the “low” portion of thefast clock, the first pulse does not occur until point D. Suchsynchronization can be insured by the addition of known circuitry.

FIG. 7 is a block diagram of a fifth embodiment of the invention.Although only the clock regulation unit 20 is illustrated in FIG. 7, thefifth embodiment interacts with an oscillator 22 and a microprocessor 2as did the third and fourth embodiments. In this embodiment, the clockregulation unit 20 includes a first divider 40 which divides the inputclock (fast clock) to produce a sleep clock, and a second divider 42which divides the input clock to produce a normal clock. The threeclocks (sleep, normal and fast) are then supplied to a selector 44. Theselector 44 outputs one of the three clocks as the output clock for themicroprocessor 2 based on first and second select inputs IN1 and IN2.The first select input IN1 is generated by inverting the digital outputfrom the temperature sensor 4 using an inverter 46. The second selectinput IN2 is generated by an activity detector 48 which functionssimilarly to the activity detector 12 in previous embodiments.

The activity detector 48 receives a plurality of activity inputs ACT1, .. . , ACTn. For example, the activity inputs notify the activitydetector 48 whether or not activity exists. Each of the activity inputsmay, for example, indicate an interrupt, keyboard activity, modem lineactivity, I/O port activity, or processor activity. As an example, FIG.8 illustrates a schematic diagram of an embodiment of the activitydetector 48. The activity detector 48 includes a OR gate 50 whichoutputs a “1” when either the activity input ACT1 or the activity inputACT2 is “1”. If neither the activity signals ACT1 and ACT2 are “1”, thenthe OR gate 50 outputs a “1”, thereby indicating the presence ofactivity.

The following Table I illustrates the selection of one of the threeclocks by the selector 44 based on the first select input IN1 and thesecond select input IN2.

TABLE I IN1 IN2 CLK Mode 0 0 Sleep 0 1 Fast 1 0 Sleep 1 1 Normal

Note that when no activity is detected by the activity detector 48, thenthe sleep clock is output. However, when activity is detected, then thenormal clock is output if the chip temperature is “hot” and the fastclock is output if the chip temperature is not “hot”. Like previousembodiments, this embodiment prevents overheating and conserves energy.

Many alternatives can be made to the third, fourth and fifth embodimentsdiscussed above. For example, additional clocks with different clockfrequencies could be provided and selected for different temperatureranges to provide a more gradual decrease in frequency. However, if amicroprocessor has sufficient thermal heat dissipation, then even theembodiment with only two different clock frequencies (fast and sleep)may provide reasonable processing speeds even when the microprocessor isgetting hot because the switching between the clocks would be quite fastas the response of the temperature sensor 4 is very rapid because it isintegrated with the microprocessor. Further, although FIGS. 4, 5, and 7illustrate the temperature sensor 4 as resident within the clockregulation unit 20, the temperature sensor 20 need only be electricallycoupled thereto and closely thermally coupled to the microprocessor 2.

FIG. 9 is a block diagram of a sixth embodiment of the invention. Inthis embodiment, the clock (CLK) received by a microprocessor 2 iseither a sleep clock produced by an oscillator 52 or atemperature-regulated fast clock produced by a VCO 8 in accordance witha temperature signal 6 (analog) from a temperature sensor 4. Clockselection is achieved by a selector 54 based on an activity signal 14provided by an activity detector 12, 48. The VCO 8, the temperaturesensor 4 and the activity detector 12, 48 were discussed above withrespect to previous embodiments. If activity is present, thetemperature-regulated fast clock is supplied to the microprocessor 2. Onthe other hand, if no activity is detected, then the sleep clock issupplied to the microprocessor 2. The temperature regulation of the fastclock is achieved by the analog temperature signal as discussed abovewith regard to FIGS. 1 and 2.

Additionally, FIG. 9 illustrates an additional feature of the invention.Namely, FIG. 9 includes an analog-to-digital converter 56, a fancontroller 58 and a cooling fan 60. Many conventional computing systemsinclude a fan for circulating air through a computer's cabinet or add-onfans that provide air-flow on or near a microprocessor. Such add-on fanscan be activated in accordance with ambient temperature. In contrast,the invention allows more accurate temperature monitoring of themicroprocessor 2 because the temperature sensor 4 is integrated with themicroprocessor 2. In addition, the invention facilitates moresophisticated energy conservation which is particularly important forportable computing devices. The temperature signal 6 is converted todigital form by the A/D converter 56 and then supplied to the fancontroller 58. The fan controller 58 performs a pulse-width modulationoperation on a supply voltage (Vcc) so as to control the speed of thefan 60. Pulse-width modulation of the supply voltage allows the speed ofthe fan to be controlled without wasting energy. Thus, this embodimentfurther includes a temperature-activated, variable-speed fan.

In the case of a desk-top computing device, it is desirable to activatethe fan 60 just prior to the temperature where the fast clock would beregulated downward because of high chip temperature. On the other hand,in the case of a portable computing device, it is desirable to attemptto limit the use of the fan 60 as much as possible by allowing the fastclock to be gradually reduced with increasing temperature beforeutilizing the fan 60. For example, if the maximum frequency of the fastclock is 100 MHz, the fan 60 could be activated in the desk-top casebefore the frequency would be regulated (e.g., attempts to maintain 100MHz). This would eliminate or delay the reduction in the frequency ofthe fast clock. In the portable case, the fan 60 could be activatedafter the frequency of the fast clock is already decreased to 25 MHz.The fan 60 would then only be used when necessary to insure reasonableprocessing power and even then at the lowest effective speed, therebysaving battery energy to the extent possible.

Although not shown but described with reference to FIG. 6, depending onthe particular design, synchronization of the switching of the frequencymay be needed to prevent partial pulse in the clock signal. Suchsynchronization is easily implemented using well-known circuitry.Likewise, if the computing device requires a consistent clock periodduring certain events (e.g., analog-to-digital conversion), thenhysteresis or other circuitry can be added to restrict the ability ofthe frequency of the clock to be changed during certain times.

Prior embodiments operate to decrease the clock frequency of the clocksignals supplied to a microprocessor to prevent overheating and toconserve energy. FIG. 10 is a block diagram of a seventh embodiment ofthe invention. This embodiment operates to provide a burst processingmode for use under certain conditions. During certain types ofprocessing activity, a clock control unit 20 causes an overdrive clockto be supplied to a microprocessor 2. Because the overdrive clock isused only in short bursts, the frequency of the overdrive clock can andpreferably exceeds the frequency which sustained processing would permitwithout rapidly overheating.

In this embodiment, the clock control unit 20 includes a first divider62 which divides the input clock to produce a sleep clock, and a seconddivider which divides the input clock to produce a fast clock. Becausethe input clock serves as the overdrive clock, the input clock has aclock frequency that is faster than that necessary for sufficientperformance and responsiveness in most cases. The clock control unit 20also includes a selector 66, an activity detector 68, and a temperaturesensor 4. The selector 66 operates to select one of the sleep, fast oroverdrive clocks based on select inputs (IN1, IN2, IN3) it receives fromthe activity detector 68 and the temperature sensor 4. Moreparticularly, the activity detector 68 receives activity signals ACT1, .. . , ACTn which cause the activity detector 68 to generate a burstactivity signal and a normal activity signal. Certain of the activitysignals ACT trigger the burst activity signal and other activity signalstrigger the normal activity signal. The temperature sensor 4 is integralwith the microprocessor 2 and produces a digital temperature signalwhich indicates whether or not the microprocessor 2 is “hot”.

The following Table II illustrates the selection of one of the threeclocks by the selector 66 based on the first select input IN1, thesecond select input IN2, and the third select input.

TABLE II IN1 IN2 IN3 CLK Mode 0 0 0 Sleep 0 0 1 Sleep 0 1 0 Fast 0 1 1Sleep 1 0 0 Overdrive 1 0 1 Fast/Sleep 1 1 0 Overdrive 1 1 1 Fast/Sleep

Note that when no activity (either burst or normal) is detected by theactivity detector 68, then the sleep clock is output. However, whenburst activity is detected, then the overdrive clock is output if thechip temperature is not “hot” and either the fast clock or the sleepclock is output if the chip temperature is “hot”. The determination ofwhich of the fast or sleep clocks to output in this situation is adesign choice depending on the ability of the computing system todissipate heat. In fact, it may be preferred to make the selection moresophisticated in this case so that selector can make the decision usingadditional temperature information such as signals indicating particulartemperature ranges or rate at which temperature is rising. When onlynormal activity is detected, then the fast clock is output if the chiptemperature is not “hot” and the sleep clock is output if the chiptemperature is “hot”. As a modification, the second divider 64 could bereplaced with a VCO thereby using a temperature-regulated fast clock.

Like previous embodiments, this embodiment prevents overheating andconserves energy. The advantage of this embodiment is that processingwill appear more uniform or regular to a user.

There are certain times during normal execution of a program, thecomputer is caused to execute operations which are beyond or unrequestedby the program being executed. Such unrequested operations includeinterrupt processing, and data transfer to cache memory following acache miss. Using the overdrive clock in these types of situations isadvantageous because such will substantially lessen any delay induced bythese unrequested operations. A computer user then perceives that thecomputer's responsiveness is more regular and uniform. For example, whena cache miss occurs an instruction currently being in process is notallowed to complete until the appropriate data block is loaded into thecache. The loading of the cache following a cache miss causes themicroprocessor to execute many operations for memory management thatwere not requested by the computer program or the user, thereby delayingthe execution of the instruction. However, because the inventionperforms such unrequested operations at higher speeds (overdrive clock),the impact of having to perform the extra unrequested operations issubstantially lessened and hopefully invisible.

In fact, a particular computer instruction could be used to indirectlyselect the desired clock frequency for the instruction. This could beuseful for instructions that require more intensive processing than donormal instructions. An example of intensive processing is complexfloating point computations. Here, the microprocessor would indicate tothe activity detector that the overdrive clock is to be used if the chiptemperature is not too “hot”.

Yet another embodiment would be to alter processing frequency forextremely cold situations. Namely, if the temperature sensor indicatesthat the chip temperature (could also use ambient temperature) is lessthan a predetermined minimum temperature, then the clock frequency couldby set regardless of activity to its maximum value to thereby cause thegeneration of as much heat as possible so that the computing devicecould operate correctly even in extremely cold conditions. Any coolingfan of the computing device would also be shut-off using a fancontroller such as shown in FIG. 9.

The many features and advantages of the present invention are apparentfrom the written description and thus it is intended by the appendedclaims to cover all such features and advantages of the invention.Further, since numerous modifications and changes will readily occur tothose skilled in the art, it is not desired to limit the invention tothe exact construction and operation as illustrated and described.Hence, all suitable modifications and equivalents may be resorted to asfalling within the scope of the invention.

What is claimed is:
 1. A method for managing operation of a computingapparatus, the computing apparatus including at least a microprocessorand a fan, the fan being operable to cool at least the microprocessor,said method comprising: configuring the computing apparatus for one of aplurality of different power management configurations; monitoring atemperature of the microprocessor; controlling a speed of the fan basedon the configured power management configuration for the computingapparatus and based on the monitored temperature of the microprocessor;and controlling an operational performance of the microprocessor basedon the configured power management configuration for the computingapparatus and based on the monitored temperature of the microprocessor,wherein said controlling the speed of the fan comprises: activating thefan to a first speed based on the configured power managementconfiguration when the monitored temperature indicates that primarythermal management is required; and subsequently increasing the speed ofthe fan to a second speed based on the configured power managementconfiguration when the monitored temperature indicates that primarythermal management is still required even after the fan has beenactivated at the first speed, the second speed being greater than thefirst speed.
 2. A method as recited in claim 1, wherein the methodcomprises: thereafter limiting operational performance of themicroprocessor when the monitored temperature indicates thatsupplemental thermal management is required even after the fan has beenactivated to the first speed.
 3. A method as recited in claim 1, whereinthe method comprises: thereafter reducing operational performance of themicroprocessor when the monitored temperature indicates thatsupplemental thermal management is required even after the fan has beenincreased to the second speed.
 4. A method as recited in claim 1,wherein the microprocessor can enter a reduced power mode, and whereinsaid method further comprises deactivating the fan when themicroprocessor enters the reduced power mode.
 5. A method as recited inclaim 1, wherein said method further comprises determining an activityindication of the microprocessor, and wherein the operationalperformance of the microprocessor is also based on the activityindication of the microprocessor.
 6. A method for managing operation ofa computing apparatus, the computing apparatus including at least amicroprocessor and a fan, the fan being operable to cool at least themicroprocessor, said method comprising: configuring the computingapparatus for one of a plurality of different power managementconfigurations; monitoring a temperature of the microprocessor;controlling a speed of the fan based on the configured power managementconfiguration for the computing apparatus and based on the monitoredtemperature of the microprocessor; and controlling an operationalperformance of the microprocessor based on the configured powermanagement configuration for the computing apparatus and based on themonitored temperature of the microprocessor, wherein said controllingthe speed of the fan comprises: activating the fan to a first speed, andsubsequently increasing the speed of the fan to a second speed based onthe configured power management configuration in view of the monitoredtemperature, so as to provide a first thermal management, and whereinsaid controlling the operational performance of the microprocessorcomprises: limiting operational performance of the microprocessor whenat least one subsequent monitored temperature indicates that a secondthermal management is required even after the fan has been activated atthe first speed and increased to the second speed.
 7. A method asrecited in claim 6, wherein the microprocessor can enter a reduced powermode, and wherein said method further comprises deactivating the fanwhen the microprocessor enters the reduced power mode.
 8. A method asrecited in claim 6, wherein said method further comprises determining anactivity indication of the microprocessor, and wherein the operationalperformance of the microprocessor is also based on the activityindication of the microprocessor.
 9. A method as recited in claim 6,wherein the speed of the fan is controlled at least by pulse widthmodulation.
 10. A method for managing operation of a portable computer,the portable computer including at least a processor and a fan, the fanbeing operable to cool at least the processor, said method comprising:configuring the portable computer for one of a plurality of differentpower management configurations; monitoring a temperature of theprocessor; controlling a speed of the fan based on the configured powermanagement configuration for the portable computer and based on themonitored temperature of the processor; and controlling an operationalperformance of the processor based on the configured power managementconfiguration for the portable computer and based on the monitoredtemperature of the processor, wherein said method comprises: monitoringactivity of the processor; wherein said controlling the speed of the fancomprises: activating the fan when the monitored temperature and themonitored activity of the processor indicate that primary thermalmanagement is required, and wherein said controlling of the operationalperformance of the processor comprises: reducing operational clockfrequency of the processor when the monitored temperature and themonitored activity of the processor indicate that supplemental thermalmanagement is required even after the fan has been activated for primarythermal management.
 11. A method as recited in claim 10, wherein afterthe fan is initially activated, the speed of the fan is increased in agradual manner as additional primary thermal management is needed.
 12. Amethod as recited in claim 10, wherein said controlling the speed of thefan comprises: increasing the speed of the fan in a gradual manner toprovide different levels of the primary thermal management.
 13. A methodas recited in claim 10, wherein said reducing the operational clockfrequency of the processor reduces the operational clock frequency by anamount dependent on the monitored temperature and the monitored activityof the processor.
 14. A method as recited in claim 10, wherein saidreducing the operational clock frequency of the processor is performedin a gradual manner to provide different levels of the supplementalthermal management.
 15. A method as recited in claim 10, wherein the fanis a variable-speed fan, and wherein said activating the fan causes thefan to operate at a speed that is dependent on the monitored temperatureand the monitored activity of the processor.
 16. A method as recited inclaim 15, wherein when the fan is initially activated, the speed of thefan is relatively slow and the speed of the fan thereafter increases ina gradual manner when the temperature of the processor increases.
 17. Amethod as recited in claim 10, wherein the fan is a variable-speed fan,and wherein the primary thermal management operates the fan atsuccessively greater speeds to provide a plurality of different levelsof the primary thermal management.
 18. A method as recited in claim 17,wherein the level of the primary thermal management being performed isdependent on the monitored temperature and the monitored activity of theprocessor.
 19. A method as recited in claim 10, wherein the supplementalthermal management reduces the operational clock frequency of theprocessor by successively greater amounts to provide a plurality ofdifferent levels of the supplemental thermal management.
 20. A method asrecited in claim 19, wherein the level of the supplemental thermalmanagement being performed is dependent on the monitored temperature andthe monitored activity of the processor.
 21. A method for managingoperation of a portable computer, the portable computer including atleast a processor and a fan, the fan being operable to cool at least theprocessor, said method comprising: configuring the portable computer forone of a plurality of different power management configurations;monitoring a temperature of the processor; setting a speed of the fanbased on the configured power management configuration for the portablecomputer and based on the monitored temperature of the processor;setting an operational performance of the processor based on theconfigured power management configuration for the portable computer andbased on the monitored temperature of the processor; and comparing themonitored temperature of the processor with at least a firstpredetermined temperature and a second predetermined temperature, thesecond predetermined temperature being higher than the firstpredetermined temperature, wherein said setting the speed of the fancomprises: activating the fan when the monitored temperature of theprocessor exceeds the first predetermined temperature, and wherein saidsetting the operational performance of the processor comprises: reducingoperational clock frequency of the processor when the monitoredtemperature of the processor exceeds the second predeterminedtemperature.
 22. A method as recited in claim 21, wherein the fanprovides primary thermal management and reduction in the operationalclock frequency of the processor provides secondary thermal management.23. A method as recited in claim 21, wherein said method furthercomprises: increasing the operational clock frequency of the processorwhen the monitored temperature of the processor drops substantiallybelow the second predetermined temperature, provided that theoperational clock frequency was previously reduced by said reducing. 24.A method as recited in claim 23, wherein said method further comprises:deactivating the fan when the monitored temperature of the processordrops below the first predetermined temperature, provided that the fanwas previously activated by said activating.